For my second master thesis I wrote a generator of VHDL multiplier modules. Software was written in C# and allows to implement several algorithms of multiplication of inputs upto 128bits (for some cases more) and with different sign representation of input/output. I hope it can be useful for some of you guys.
My master thesis (pdf): VHDL Multiplication modules IP generator
Software project files (zip): VHDL Multiplication module IP generator software Visual Studio Project
Software installer files (zip): VHDLMultiplication module IP generator Installer
Also it allowed to create some comparison graphs of different algorithms (time in ns):
Conclusions from master thesis:
It can be deducted from given synthesis results that there is no single solution that is best in all cases. Some structures are very economical in logic resources usage, but have rather long time delay. An example of such structure is scaling accumulator multiplier. On the other hand some structures use much more resources but can produce a result in much shorter time, for example row ripple array multiplier.
The totally different category is based on memory structures. In this case, the structure can be very fast and use not that much of standard logic blocks, but instead use RAM blocks. It gives the designer a way to choose between utilization of diferent parts of FPGA- if all logic blocks are needed, the multiplication can be placed in other unused resources.
This chain of trade offs that a designer is subjected to, makes it quite important to be able to quickly test di?erent solutions and choose the most suitable one. It can be easily realized with use of this generator.