VHDL Multiplication module IP generator

User interface

For my second master thesis I wrote a generator of VHDL multiplier modules. Software was written in C# and allows to implement several algorithms of multiplication of inputs upto 128bits (for some cases more) and with different sign representation of input/output. I hope it can be useful for some of you guys.

My master thesis (pdf): VHDL Multiplication modules IP generator

Software project files (zip): VHDL Multiplication module IP generator software Visual Studio Project

Software installer files (zip): VHDLMultiplication module IP generator Installer

Also it allowed to create some comparison graphs of different algorithms (time in ns):

Resources used, slices - 2 vector

Resources used, FFs - 2 vector

Resources used, RAM - 2 vector

Time to get result - 2 vector

Time to get result - 1 vector

Time to get result - Booth reordering with constant multiplier

Simple case/simple rom generation time

Simple case/simple rom generation time

 

Memory tree generation time

Memory tree generation time

Conclusions from master thesis:

It can be deducted from given synthesis results that there is no single solution that is best in all cases. Some structures are very economical in logic resources usage, but have rather long time delay. An example of such structure is scaling accumulator multiplier. On the other hand some structures use much more resources but can produce a result in much shorter time, for example row ripple array multiplier.
The totally different category is based on memory structures. In this case, the structure can be very fast and use not that much of standard logic blocks, but instead use RAM blocks. It gives the designer a way to choose between utilization of diferent parts of FPGA- if all logic blocks are needed, the multiplication can be placed in other unused resources.

This chain of trade offs that a designer is subjected to, makes it quite important to be able to quickly test di?erent solutions and choose the most suitable one. It can be easily realized with use of this generator.

Category(s): Electrical engineering
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  4. There is a bug. In some cases the top bits of the result are not set.
    For example:
    (Const) Row Ripple Array
    Bits in A 19
    Constant 640
    A sign 2′s complement
    Output sign 2′s complement
    This is what is produced:

    entity main_unit is
    port(
    a : IN STD_LOGIC_VECTOR(19-1 DOWNTO 0);
    y : OUT STD_LOGIC_VECTOR(29-1 DOWNTO 0)
    );
    ……………..
    y(26) <= sig2(17);
    y(27) <= sig2(1Smilie: 8);
    end Behavioral;

    Bit 28 is not set.

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